AbhyasaSEMICON TECHNOLOGIES

Trimming a Design in Innovus (trimDesign)

Efficiently manage large VLSI designs with trimDesign.

In semiconductor design, it is not always practical to share the entire design, especially when it contains third-party IP data. Instead, a trimmed version of the design can be created, allowing engineers to focus on a smaller portion while maintaining confidentiality. The trimDesign command in Innovus facilitates this by extracting a specific section of the layout while retaining essential physical data. This approach significantly reduces memory usage and enhances debugging efficiency

Benefits of trimDesign

  • Enables engineers to debug and analyze smaller sections independently.
  • Retains all placement and routing violations (checkPlace and verify_drc).
  • Maintains crucial design elements like instances, macros, routing/placement blockages, and wire attributes.
  • Eliminates hierarchical information for confidentiality.
  • Encrypts object names for added data protection (customizable options).
  • Reduces memory footprint and improves turnaround time for analysis

Working of trimDesign

The trimDesign process extracts a defined portion of a larger design by specifying a coordinate box. The extracted section retains its physical attributes while discarding timing and power domain data. However, since it remains physically equivalent to the original design, it allows for meaningful placement and DRC verification. The LEF file must be shared alongside the trimmed design for proper placement and DRC verification

The selected box becomes an independent design. A hard macro overlapping its boundary remains at the same relative position; objects wholly outside are excluded.
Selected trim area, including an overlapping hard macro, and the resulting independent design
trimDesign –dir DB –name trim_db –area {300.0 200.0 900.0 700.0}
trimDesign –selectedRouteBlk
trimDesign –dir DB –name trim_db –area {300.0 200.0 800.0 700.0} -encryptName gen_new_name

During the trim process, the specified trim box/area is snapped to the instance grid. All instances in the selected area lose their original logic hierarchy and appear flat in the new database. Any naming conflicts arising due to flattening are resolved automatically, with a mapping file generated for reference. Additionally, trimDesign does not save binary data; instead, it stores DEF, Verilog, and LEF information in .txt format.

What Happens with the Trimmed Design?

  • Permanent Modification: Once a design is trimmed, it cannot be reconstructed back into the original design. Attempting to merge it back is not supported.
  • Flattened Structure: Instances within the trim area lose their original hierarchy and appear flat.
  • Violation Preservation: The checkPlace and verify_drc commands will still detect the same placement and DRC violations, except for those related to hierarchical constraints
  • Possible Additional DRC Violations: Some minor extra violations may appear due to boundary conditions in net wire preservation
  • Automated Naming Adjustments: Instance and net names are automatically modified if conflicts arise, with a mapping file created for reference.
  • Saving the data: The trimDesign does not save binary data; instead, it stores DEF, Verilog, and LEF information in .txt format.
Cadence guide example: two original instance paths, h1/h2/i1 and h1/h4/i1, map to flat names i1 and i1_uniquify1; a map file records the changes.
Flattened instance names and the generated mapping file

Key Aspects of the Trimmed Design

  • Instances and Macros: Instances inside the trim area retain attributes, but hierarchical information is lost. Hard macros overlapping the trim area are preserved.
  • Naming Conflicts & Encryption: Flattening the hierarchy may cause name conflicts, which are resolved automatically with unique suffixes. A mapping file is generated to track original versus modified names.
  • Nets and Wires: Nets with instances inside the trim area are retained, while those fully outside are discarded. Ports are created for wires crossing the boundary.
  • Physical Data Integrity: The process preserves regular/special wires, routing blockages, tracks, sites, rows, and overlapping colors within the trim area.
  • Loss of Hierarchical Information: Since the trim process flattens the design, hierarchical fences, instance groups, and power domains are discarded.
Before and after trimming: an inside cell and its crossing wire are retained with a new port at the trim boundary; a separate wholly outside net is omitted.
Crossing wire and wholly outside net before and after trimming

Limitations & Considerations

  • Non-Reversible Process: : The trimmed design cannot be restored or reintegrated into the original design.
  • Flattened Hierarchy: Instances within the trim area lose their original hierarchical structure.
  • Boundary Condition Effects: Some additional DRC violations may emerge due to the preservation of only certain net wires crossing the trim area.
  • Exclusion of Certain Design Features: The trimming process does not retain fences, regions, guides, instance groups, and power domains.
  • LEF File Requirement: The trimmed design requires the LEF technology file for correct placement and DRC verification.
  • Modified Naming Scheme: Encrypted or altered instance and net names require a mapping file for proper tracking.

Conclusion

The trimDesign command in Innovus is an essential tool for handling large-scale VLSI designs efficiently. It allows engineers to isolate and analyze smaller sections while maintaining physical design integrity and confidentiality. By leveraging this functionality, debugging is accelerated, memory usage is reduced, and third-party IP protection is ensured, making it a valuable feature for modern semiconductor design workflows.

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